View CAT661_1814112.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features converts v+ to v- or v+ to 2v+ low output resistance, 10 ? max. high power efficiency selectable charge pump frequency of 25khz or 135khz; optimize capacitor size. low quiescent current description the CAT661 is a charge-pump voltage converter. it can invert a positive input voltage to a negative output. only two external capacitors are needed. with a guaranteed 100ma output current capability, the CAT661 can replace a switching regulator and its inductor. lower emi is achieved due to the absence of an inductor. in addition, the CAT661 can double a voltage supplied from a battery or power supply. inputs from 2.5v to 5.5v will yield a doubled, 5v to 11v output. a frequency control pin (boost/fc) is provided to select either a high (typically 135khz) or low (25khz) internal oscillator frequency, thus allowing quiescent current vs. capacitor size trade-offs to be made. the 135khz frequency is selected when the fc pin is CAT661 high frequency 100ma cmos charge pump, inverter/doubler pin-compatible to max660, ltc660 with higher frequency operation available in 8-pin soic anddip packages lead-free, halogen-free package option ?catalyst semiconductor, inc. characteristics subject to change without notice doc. no. md-5003, rev. k applications negative voltage generator voltage doubler voltage splitter low emi power source gaas fet biasing lithium battery power supply instrumentation lcd contrast bias cellular phones, pagers typical application connected to v+. the operating frequency can also be adjusted with an external capacitor at the osc pin or by driving osc with an external clock. both 8-pin dip and so packages are available. for die availability, contact catalyst semiconductor marketing. the CAT661 can replace the max660 and the ltc660 in applications where higher oscillator frequency and smaller capacitors are needed. in addition, the CAT661 is pin compatible with the 7660/1044, offering an easy upgrade for applications with 100ma loads. h a l o g e n f r e e tm l e a d f r e e 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out CAT661 +v in 1.5v to 5.5v inverted negative voltage output + voltage inverter 8 7 6 5 1 2 3 4 doubled positive voltage output + v in = 2.5v to 5.5v boost/fc cap+ gnd cap- v+ osc lv out CAT661 positive voltage doubler c1 c1
CAT661 2 doc. no. md-5003, rev. k oscillator frequency 25khz typical, 10khz minimum 135khz typical, 80khz minimum pin configuration pin descriptions circuit configuration pin number name inverter doubler boost/fc oscillator frequency open 40khz typical v+ 135khz typical, 40khz minimum 2 cap+ charge pump capacitor. positive terminal. same as inverter. 3 gnd power supply ground. power supply. positive voltage input. 4 cap- charge pump capacitor. negative terminal. same as inverter. 5 out output for negative voltage. power supply ground. 6 lv lv must be tied to out for all input voltages. 8 v+ power supply. positive voltage input. positive voltage output. freqency control for the internal oscillator. with an external oscillator boost/fc has no effect. same as inverter. low-voltage selection pin. when the input voltage is less than 3v, connect lv to gnd. for input voltages above 3v, lv may be connected to gnd or left open. if osc is driven externally, connect lv to gnd. oscillator control input. an external capacitor can be connected to lower the oscillator frequency. an external oscillator can drive osc and set the chip operating frequency. the charge-pump frequency is one-half the frequency at osc. same as inverter. do not overdrive osc in doubling mode. standard logic levels will not be suitable. see the applications section for additional information. 7 osc 1 boost/fc soic 8-lead (v) pdip 8-lead (l) 8 7 6 5 1 2 3 4 boost/fc cap+ gnd cap- v+ osc lv out CAT661 (top view) ordering information r e b m u n t r a pe g a k c a py t i n a u q e g a k c a p g n i k r a m a l e 1 6 6 t a cd a e l - 8 , p i d pe b u t / 0 5a l e 1 6 6 a v e 1 6 6 t a cc i o se b u t / 0 0 1a v e 1 6 6 3 t - a v e 1 6 6 t a cc i o sl e e r / 0 0 0 , 3a v e 1 6 6 note: all packages are rohs compliant.
CAT661 3 doc. no. md-5003, rev. k absolute maximum ratings v+ to gnd ............................................................. 6v input voltage (pins 1, 6 and 7) .. -0.3v to (v+ + 0.3v) boost/fc and osc input voltage ........... the least negative of (out - 0.3v) or (v+ - 6v) to (v+ + 0.3v) output short-circuit duration to gnd .............. 1 sec. (out may be shorted to gnd for 1 sec without damage but shorting out to v+ should be avoided.) continuous power dissipation (t a = 70 c) plastic dip ................................................ 730mw so ............................................................ 500mw tdfn ............................................................... 1w operating ambient temperature ranges CAT661e .............. -40 c to 85 c storage temperature ......................... -65 c to 160 c lead soldering temperature (10 sec) ............. 300 c esd rating-human body model ..................... 2000v note: t a = ambient temperature these are stress ratings only and functional operation is not implied. exposure to absolute maximum ratings for prolongued time periods may affect device reliability. all voltages are with respect to ground. parameter symbol conditions min. typ max. units inverter: lv = open. r l = 1k ? 3.0 5.5 v supply voltage vs inverter: lv = gnd. r l = 1k ? 1.5 5.5 doubler: lv = out. r l = 1k ? 2.5 5.5 supply current is boost/fc = open, lv = open 0.2 0.5 ma boost/fc = v+ , lv = open 1 3 output current iout out is more negative than -4v 100 ma output resistance ro c1 = c2 = 10 f, 3.5 10 ? boost/fc = v+ (c1, c2 esr 0.5 ? ) c1 = c2 = 100 f (note 2) 3.5 10 oscillator frequency fosc boost/fc = open 10 25 khz (note 3) boost/fc = v+ 80 135 osc input current iosc boost/fc = open 2 a boost/fc = v+ 10 power efficiency pe r l = 1k ? connected between v+ and 96 98 % out, t a = 25 c (doubler) r l = 500 ? connected between gnd and 92 96 out, t a = 25 c (inverter) i l = 100ma to gnd, t a = 25 c (inverter) 88 voltage conversion veff no load, t a = 25 c 99 99.9 % efficiency 1. in figure 1, test circuit electrolytic capacitors c1 and c2 are 100 f and have 0.2 ? maximum esr. higher esr levels may reduce efficiency and output voltage. 2. the output resistance is a combination of the internal switch resistance and the external capacitor esr. for maximum voltage and efficiency keep external capacitor esr under 0.2 ? . 3. fosc is tested with c osc = 100pf to minimize test fixture loading. the test is correlated back to c osc =0pf to simulate the capacitance at osc when the device is inserted into a test socket without an external c osc . electrical characteristics v+ = 5v, c1 = c2 = 100 f, boost/fc = open, c osc = 0pf, and test circuit is figure 1 unless otherwise noted. temperature is t a = t amin to t amax unless otherwise noted.
CAT661 4 doc. no. md-5003, rev. k typical operating characteristics typical characteristic curves are generated using the circuit in figure 1. inverter test conditions are: v+ 5v, lv = gnd, boost/fc = open and t a = 25?c unless otherwise indicated. note that the charge-pump frequency is one-half the oscillator frequency. figure 1. test circuit voltage inverter 1 2 3 4 8 7 6 5 CAT661 external oscillator c osc r l c2 100f + v + 5v i s v + + c 1 100f i l v ou t boost/fc cap+ gnd cap- v+ osc lv out 0 2 4 6 8 10 123456 input voltage [v] 0 200 400 600 800 1000 1200 1400 123456 input voltage [v] fc = open fc = v+ 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 vin = 5v vin = 2v vin = 3v supply current vs. input voltage supply current vs. temperature (no load) output resistance vs. input voltage output resistance vs. temperature (50 ? load) output resistance [ ? ] output resistance [ ? ] input current [ a] input current [ a] temperature [ o c] temperature [ o c] 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 vin = 2v vin = 3v vin = 5v
CAT661 5 doc. no. md-5003, rev. k typical operating characteristics 4.0 4.2 4.4 4.6 4.8 5.0 0 20406080100 load current [ma] 0.0 0.2 0.4 0.6 0.8 1.0 0 2040 6080100 load current [ma] v+ = 3v v+ = 5 v inverted output voltage vs. load, v+ = 5v output voltage drop vs. load current 0 40 80 120 160 200 12 34 56 supply voltage [v] fc = v+ 0 10 20 30 40 50 12 34 56 supply voltage [v] fc = open 40 50 60 70 80 90 100 0 50 100 load current [ma] v+ = 3v v+ =5v oscillator frequency vs. supply voltage oscillator frequency vs. supply voltage supply current vs. oscillator frequency efficiency vs. load current efficiency [%] input current [ a] frequency [khz] frequency [khz] output voltage [v] inv. output voltage [v] 10 100 1000 1 0000 1 10 100 1000 oscillator frequency [khz] no ld no load
CAT661 6 doc. no. md-5003, rev. k typical operating characteristics typical characteristic curves are generated using the circuit in figure 2. doubler test conditions are: v+ 5v, lv = gnd, boost/fc = open and t a = 25 ? c unless otherwise indicated. figure 2. test circuit voltage doubler 1 2 3 4 8 7 6 5 CAT661 external oscillator c2 100f 10v v ou t v + + c 1 100f boost/fc cap+ gnd cap- v+ osc lv out v+ 5v 0 500 1000 1500 2000 2500 3000 0123456 input voltage [v] fc = open fc = v+ 0 2 4 6 8 10 123456 input voltage [v] 0.0 0.2 0.4 0.6 0.8 1.0 0 20406080100 load current [ma] v+ = 3v v+ = 5v 10 100 1000 10000 1 10 100 1000 oscillator frequency [khz] no load supply current vs. input voltage (no load) output resistance vs. input voltage supply current vs. oscillator frequency output voltage drop vs. load current output voltage [v] input current [ a] output resistance [ ? ] input current [ a]
CAT661 7 doc. no. md-5003, rev. k the 1/fc1 term can be modeled as an equivalent impedance req. a simple equivalent circuit is shown in figure 4. this circuit does not include the switch resistance nor does it include output voltage ripple. it does allow one to understand the switch-capacitor topology and make prudent engineering tradeoffs. for example, power conversion efficiency is set by the output impedance, which consists of req and switch resistance. as switching frequency is decreased, req, the 1/fc1 term, will dominate the output impedance, causing higher voltage losses and decreased efficiency. as the frequency is increased quiescent current increases. at high frequency this current becomes significant and the power efficiency degrades. the oscillator is designed to operate where voltage losses are a minimum. with external 150 f capacitors, the internal switch resistances and the equivalent series resistance (esr) of the external capacitors determine the effective output impedance. a block diagram of the CAT661 is shown in figure 5. figure 3. switched-capacitor building block figure 4. switched-capacitor equivalent circuit application information circuit description and operating theory the CAT661 switches capacitors to invert or double an input voltage. figure 3 shows a simple switch capacitor circuit. in position 1 capacitor c1 is charged to voltage v1. the total charge on c1 is q1 = c1v1. when the switch moves to position 2, the input capacitor c1 is discharged to voltage v2. after discharge, the charge on c1 is q2 = c1v2. the charge transferred is: ? q = q1 - q2 = c1 (v1 - v2) if the switch is cycled "f" times per second, the current (charge transfer per unit time) is: i = f ? q = f c1 (v1 - v2) rearranging in terms of impedance: i= (v1-v2) v1-v2 (1/fc1) req = v1 c1 c2 r l v2 v1 c2 r l v2 req req = 1 fc1
CAT661 8 doc. no. md-5003, rev. k figure 5. CAT661 block diagram + c2 v + (8) 2 osc boost/fc 8x (1) osc (7) lv (6) closed when v + > 3.0v gnd (3) cap - (4) c1 + cap + (2) sw2 sw1 vout (5) (n) = pin number oscillator frequency control the switching frequency can be raised, lowered or driven from an external source. figure 6 shows a functional diagram of the oscillator circuit. the CAT661 oscillator has four control modes: boost/fc pin connection osc pin connection nominal oscillator frequency open open 25khz boost/fc= v+ open 135khz open or boost/fc= v+ external capacitor open external clock frequency of external clock if boost/fc and osc are left floating (open), the nominal oscillator frequency is 25khz. the pump frequency is one-half the oscillator frequency. by connecting the boost/fc pin to v+, the charge and discharge currents are increased, and the frequency is increased by approximately 6 times. increasing the frequency will decrease the output impedance and ripple currents. this can be an advantage at high load currents. increasing the frequency raises quiescent current but allows smaller capacitance values for c1 and c2. if pin 7, osc, is loaded with an external capacitor the frequency is lowered. by using the boost/fc pin and an external capacitor at osc, the operating frequency can be set. note that the frequency appearing at cap+ or cap- is one-half that of the oscillator. driving the CAT661 from an external frequency source can be easily achieved by driving pin 7 and leaving the boost pin open, as shown in figure 6. the output current from pin 7 is small, typically 1 a to 8 a, so a cmos can drive the osc pin. for 5v applications, a ttl logic gate can be used if an external 100k ? pull-up resistor is used as shown in figure 7.
CAT661 9 doc. no. md-5003, rev. k vripple (mv) iout (ma) fosc (khz) c2 ( f) c2 esr ( ? ) 45 100 25 150 0.2 25 100 135 150 0.2 capacitor selection low esr capacitors are necessary to minimize voltage losses, especially at high load currents. the exact values of c1 and c2 are not critical but low esr capacitors are necessary. the esr of capacitor c1, the pump capacitor, can have a pronounced effect on the output. c1 currents are approximately twice the output current and losses occur on both the charge and discharge cycle. the esr effects are thus multiplied by four. a 0.5 ? esr for c1 will have the same effect as a 2 ? increase in CAT661 output impedance. output voltage ripple is determined by the value of c2 and the load current. c2 is charged and discharged at a current roughly equal to the load current. the internal switching frequency is one-half the oscillator frequency. vripple = iout/(fosc x c2) + iout x esrc2 for example, with a 25khz oscillator frequency (12.5khz switching frequency), a 150 f c2 capacitor with an esr of 0.2 ? and a 100ma load peak-to-peak the ripple voltage is 45mv. vripple vs. fosc figure 6. oscillator figure 7. external clocking boost/fc (1) lv (6) osc (7) ~18pf i 7.0 i 7.0 i i v + + -v + c2 1 2 3 4 8 7 6 5 required for ttl logic CAT661 v + 100k osc input nc + c1 boost/fc cap+ gnd cap- v+ osc lv out
CAT661 10 doc. no. md-5003, rev. k capacitor suppliers the following manufacturers supply low-esr capacitors: manufacturer capacitor type phone web email comments avx/kyocera tps/tps3 843-448-9411 www.avxcorp.com avx@avxcorp.com tantalum vishay/sprague 595 402-563-6866 www.vishay.com aluminum sanyo mv-ax, ugx 619-661-6835 www.sanyo.com svcsales@sanyo.com aluminum nichicon f55 847-843-7500 www.nichicon-us.com tantalum hc/hd aluminum the effective output impedance of a CAT661 circuit is approximately: rcircuit rout 661 + (4 x esrc1) + esrc2 voltage inversion positive-to-negative the CAT661 easily provides a negative supply voltage from a positive supply in the system. figure 8 shows a typical circuit. the lv pin may be left floating for positive input voltages at or above 3.3v. figure 8: voltage inverter controlling loss in CAT661 applications there are three primary sources of voltage loss: 1. output resistance vloss = iload x rout, where rout is the CAT661 output resistance and iload is the load current. 2. charge pump (c1) capacitor esr: vlossc1 4 x esrc1 x iload, where esrc1 is the esr of capacitor c1. 3. output or reservoir (c2) capacitor esr: vlossc2 = esrc2 x iload, where esrc2 is the esr of capacitor c2. increasing the value of c2 and/or decreasing its esr will reduce noise and ripple. + v out = -v in c2 1 2 3 4 8 7 6 5 CAT661 nc + c1 v in 1.5v to 5.5v boost/fc cap+ gnd cap- v+ osc lv out capacitor manufacturers continually introduce new series and offer different package styles. it is recommended that before a design is finalized capacitor manufacturers should be surveyed for their latest product offerings. typical applications
CAT661 11 doc. no. md-5003, rev. k positive voltage doubler the voltage doubler circuit shown in figure 9 gives vout = 2 x vin for input voltages from 2.5v to 5.5v. precision voltage divider a precision voltage divider is shown in figure 10. with load currents under 100na, the voltage at pin 2 will be within 0.002% of v+/2 . figure 9: voltage doubler figure 10: precision voltage divider (load 100na) 1 2 3 4 8 7 6 5 CAT661 + boost/fc cap+ gnd cap- v out = 2v in + v in 2.5v to 5.5v 1n5817* *schottky diode is for start-up only v+ osc lv out 1 2 3 4 8 7 6 5 + v + 3v to 11v + boost/fc cap+ gnd cap- v+ osc lv out CAT661 + 0.002% v + 2 i l < 100na
CAT661 12 doc. no. md-5003, rev. k battery voltage splitter positive and negative voltages that track each other can be obtained from a battery. figure 11 shows how a 9v battery can provide symmetrical positive and negative voltages equal to one-half the battery voltage. cascade operation for higher negative voltages the CAT661 can be cascaded as shown in figure 12 to generate more negative voltage levels. the output resistance is approximately the sum of the individual CAT661 output resistance. v out = -n x v in , where n represents the number of cascaded devices. figure 11: battery splitter figure 12: cascading to increase output voltage + - (-4.5v) 1 2 3 4 8 7 6 5 CAT661 + boost/fc cap+ gnd cap- v+ osc lv out + (4.5v) 3v < v bat < 11v v bat 9v battery v bat 2 v bat 2 + c2 2 3 4 8 5 CAT661 "1" + c1 + CAT661 "n" 2 3 4 8 5 c1n +v in + c2 v out = -nv in
CAT661 13 doc. no. md-5003, rev. k parallel operation paralleling CAT661 devices will lower output resistance. as shown in figure 13, each device requires its own pump capacitor, c2, but the output reservoir capacitor is shared with all devices. the value of c2 should be increased by a factor of n, where n is the number of devices. figure 13: reduce output resistance by paralleling devices + c2 2 3 4 8 5 CAT661 "1" + c1 + CAT661 "n" 2 3 4 8 5 c1n +v in rout = rout (of CAT661) n (number of devices)
CAT661 14 doc. no. md-5003, rev. k soic 8-lead 150mils (v) notes: 1. al dimensions are in millimeters. angles in degrees. 2. complies with jedec standard ms-012. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 5.80 6.20 e1 3.80 4.00 e 1.27 bsc h 0.25 0.50 l 0.40 1.27 0o 8o symbol min nom max for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. package outline drawings
CAT661 15 doc. no. md-5003, rev. k pdip 8-lead 300mils (l) e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification symbol min nom max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80 notes: 1. al dimensions are in millimeters. angles in degrees. 2. complies with jedec standard ms-001. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT661 16 doc. no. md-5003, rev. k 661 prefix device # suffix eva t3 product number 661 tape & reel t: tape & reel 3: 3000/reel package ela: pdip eva: soic cat optional company id notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead finish is matte-tin. (3) the device used in the above example is a CAT661w-t3 (soic, tape & reel). example of ordering information
date rev. reason 10/15/03 g updated description - eliminated commercial temperature range 10/27/04 h minor changes throughout data sheet 1/20/2005 i changed ordering information for CAT661exa to CAT661eva changed ordering information for CAT661exa-te13 to CAT661eva-te13 04/22/2005 j removed preliminary information from data sheet header 11/16/2007 k update features and description update package outline drawings and remove tdfn add example of ordering information add ordering part number add "md-" to document number catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: md-5003 revison: k issue date: 11/16/07 revision history copyrights, trademarks and patents ?catalyst semiconductor, inc. trademarks and registered trademarks of catalyst semiconductor include each of the following: adaptive analog, beyond memory, dpp, ezdim, ldd, minipot, quad-mode and quantum charge programmable catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

▲Up To Search▲

Price & Availability of CAT661

	To Download CAT661 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .